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19-1789; Rev 1; 10/02
Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable
General Description
The MAX9691/MAX9692/MAX9693 are ultra-fast ECL comparators capable of very short propagation delays. Their design maintains the excellent DC matching characteristics normally found only in slower comparators. The MAX9691/MAX9692/MAX9693 have differential inputs and complementary outputs that are fully compatible with ECL-logic levels. Output current levels are capable of driving 50 terminated transmission lines. The ultra-fast operation makes signal processing possible at frequencies in excess of 600MHz. The MAX9692/MAX9693 feature a latch-enable (LE) function that allows the comparator to be used in a sample-hold mode. When LE is ECL high, the comparator functions normally. When LE is driven ECL low, the outputs are forced to an unambiguous ECL-logic state, dependent on the input conditions at the time of the latch input transition. If the latch-enable function is not used on either of the two comparators, the appropriate LE input must be connected to ground; the companion LE input must be connected to a high ECL logic level. These devices are available in SO, QSOP, and tiny MAX packages for added space savings. o 1.2ns Propagation Delay o 100ps Propagation Delay Skew o 150ps Dispersion o 0.5ns Latch Setup Time o 0.5ns Latch-Enable Pulse Width o Available in MAX and QSOP Packages o +5V, -5.2V Power Supplies
Features
MAX9691/MAX9692/MAX9693
Ordering Information
PART MAX9691EUA MAX9691ESA MAX9691EPA TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 8 MAX 8 SO 8 PDIP
Ordering Information continued at the end of data sheet.
Selector Guide
PART MAX9691 MAX9692 COMPARATORS PER PACKAGE 1 1 LATCH ENABLE No Yes PINPACKAGE 8 MAX, 8 SO, 8 PDIP 10 MAX, 16 SO, 16 PDIP 16 QSOP, 16 SO, 16 PDIP
________________________Applications
High-Speed Line Receivers Peak Detectors Threshold Detectors High-Speed Triggers
MAX9693
2
Yes
Pin Configurations appear at end of data sheet.
_________________________________________________________Functional Diagrams
IN+ Q OUT NONINVERTING INPUT Q OUT INVERTING INPUT INVERTING INPUT NONINVERTING INPUT
INRL MAX9691 VT RL
Q OUT
Q OUT RL LE LE RL RL RL LE LE VT
MAX9693
MAX9693
LATCH ENABLE
LATCH ENABLE
THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULLDOWN RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50 TO 200 CONNECTED TO -2.0V, OR 240 TO 2000 CONNECTED TO -5.2V.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable MAX9691/MAX9692/MAX9693
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ...............................................-0.3V to +6V Supply Voltage (VEE)................................................-6V to +0.3V Input Voltage....................................(VCC + 0.3V) to (VEE - 0.3V) Output Short-Circuit Duration ....................................Continuous Differential Input Voltage ......................................................5V Latch Enable ...............................................(VEE - 0.3V) to +0.3V Output Current ....................................................................50mA Input Current ....................................................................25mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.1mW/C above 70C)...............330mW 8-Pin SO (derate 5.88mW/C above +70C) ...............471mW 8-Pin PDIP (derate 10.53mW/C above +70C)...........842mW 10-Pin MAX (derate 5.6mW/C above +70C)...........444mW 16-Pin QSOP (derate 8.3mW/C above +70C) ..........667mW 16-Pin SO (derate 8.7mW/C above +70C) ...............696mW 16-Pin PDIP (derate 9.09mW/C above +70C) ..........727mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V, VEE = -5.2V, RL = 50 to VT, VT = -2V, LE = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER Input Offset Voltage Temperature Coefficient Input Offset Current Input Bias Current Input Voltage Range Common-Mode Rejection Ratio Positive Power-Supply Rejection Ratio Negative Power-Supply Rejection Ratio Open-Loop Gain Differential Input Resistance Differential Input Clamp Voltage Input Capacitance Latch Enable Input Current High Latch Enable Input Current Low Latch Enable Logic High Voltage Latch Enable Logic Low Voltage Logic Output High Voltage CIN IIH(LE) IIL(LE) VIH(LE) VIL(LE) TA = TMIN VOH TA = TMAX TA = +25C TA = TMIN Logic Output Low Voltage VOL TA = TMAX TA = +25C -1.2 -0.99 -1.06 -1.93 -1.89 -1.89 VIH(LE) = 1.1V VIL(LE) = 1.5V -1.1 -1.5 -0.87 -0.70 -0.76 -1.57 -1.51 -1.55 V V SYMBOL VOS VOS/T IOS IB VCM CMRR +PSRR -PSRR AOL RIN TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX Note 1 -2.5V VCM +3.0V (Note 1) 4.5V VCC 5.5V -5.7V VEE -4.7V VCM = 0V -10mV < VIN < 10mV -2.5 60 80 60 60 70 60 1.7 3 60 0.2 120 10 6 TA = +25C TA = TMIN to TMAX CONDITIONS MIN -6.5 -11.5 10 0.2 5 8 20 30 +3.0 TYP MAX 6.5 +11.5 UNITS mV V/C A A V dB dB dB dB k V pF A A V V
2
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Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, VEE = -5.2V, RL = 50 to VT, VT = -2V, LE = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL MAX9693 Supply Current ICC MAX9691/ MAX9692 CONDITIONS TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX 18 MIN TYP 34 MAX 46 50 26 36 mA UNITS
MAX9691/MAX9692/MAX9693
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V, VEE = -5.2V, RL = 50 to VT, VT = -2V, LE = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER MAX9691/MAX9692/MAX9693 Propagation Delay (Notes 1, 2) Rise/Fall Time Propagation Delay Skew Dispersion MAX9692/MAX9693 Latch-Enable Time (Note 1) Latch-Enable Pulse Width (Note 1) Setup Time (Note 1) Hold Time (Note 1) Channel-to-Channel Propagation Match TLE() tpw(LE) ts th tPDM Note 2 (MAX9693 only) TA = +25C TA = TMIN to TMAX 0.5 0.5 0.5 100 1.0 1.8 2.0 1.0 1.0 1.0 ns ns ns ns ps tpd+, tpdtr, tf PD PDSP VOD from 10mV to 100mV TA = +25C TA = TMIN to TMAX 10% to 90% 500 100 150 1.2 1.8 2.0 ns ps ps ps SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Guaranteed by design. Note 2: VIN = 100mV, VOD = 10mV.
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Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable MAX9691/MAX9692/MAX9693
Typical Operating Characteristics
(VCC = +5V, VEE = -5.2V, RL = 50 to VT, VT = -2V, VOD = 10mV, TA = +25C, unless otherwise noted.)
WORST-CASE PROPAGATION DELAY vs. INPUT OVERDRIVE
MAX9691/3-01
WORST-CASE PROPAGATION DELAY vs. SOURCE IMPEDANCE
MAX9691/3-02
WORST-CASE PROPAGATION DELAY vs. CLOAD
MAX9691/3-03
1400
6000 5000 PROPAGATION DELAY (ps) 4000 3000 2000 1000 0
1800 1600 PROPAGATION DELAY (ps) 1400 1200 1000 800 600
PROPAGATION DELAY (ps)
1200
1000
800
600
400 0 10 20 30 40 50 60 70 80 90 100 INPUT OVERDRIVE (mV)
0
50 100 150 200 250 300 350 400 450 500 SOURCE IMPEDANCE ()
0
5
10
15
20
25
CLOAD (pF)
WORST-CASE PROPAGATION DELAY vs. TEMPERATURE
MAX9691/3-04
OUTPUT HIGH VOLTAGE vs. TEMPERATURE
MAX9691/3-05
OUTPUT LOW VOLTAGE vs. TEMPERATURE
-1.62 -1.64 -1.66 VOL (V) -1.68 -1.70 -1.72 RPULLDOWN = 200 RPULLDOWN = 100
MAX9691/3-06
1400 1300 PROPAGATION DELAY (ps) 1200 1100 1000 900 800 700 VOD = 100mV 600 -40 -15 10 35 60
-0.6
-1.60
-0.7 RPULLDOWN = 200
RPULLDOWN = 100
VOH (V)
-0.8
-0.9 RPULLDOWN = 50 -1.0
-1.74 -1.76 -1.78 RPULLDOWN = 50
-1.1 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
-1.80 -40 -15 10 35 60 85 TEMPERATURE (C)
INPUT OFFSET VOLTAGE vs. TEMPERATURE
MAX9691/3-08
INPUT BIAS CURRENT vs. TEMPERATURE
MAX9691/3-09
INPUT BIAS CURRENT vs. DIFFERENTIAL INPUT VOLTAGE
4000 INPUT BIAS CURRENT (A) 3000 2000 1000 0 -1000 -2000 -3000 -4000 -5000
MAX9691/3-10
2000 1500 INPUT OFFSET VOLTAGE (V) 1000 500 0 -500
8.0 7.5 INPUT BIAS CURRENT (A) 7.0 6.5 6.0 5.5 5.0 4.5 4.0
5000
-1000 -1500 -2000 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
-5
-4
-3
-2
-1
0
1
2
3
4
5
TEMPERATURE (C)
DIFFERENTIAL INPUT VOLTAGE (V)
4
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Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable
Typical Operating Characteristics (continued)
(VCC = +5V, VEE = -5.2V, RL = 50 to VT, VT = -2V, VOD = 10mV, TA = +25C, unless otherwise noted.)
MAX9691/MAX9692/MAX9693
PROPAGATION DELAY
MAX9691/3-11
100MHz OUTPUT RESPONSE
MAX9691/3-12
VIN = 100mV VOD = 10mV VIN 200mV/div Q OUT 200mV/div
-1.0V
-1.8V -1.0V Q OUT - Q OUT 200mV/div Q OUT 200mV/div
-1.8V 1ns/div 1ns/div
__________ Applications Information
Layout
Because of the MAX9691/MAX9692/MAX9693s' large gain-bandwidth characteristic, special precautions must be taken to use them. A PC board with a ground plane is mandatory. Mount 0.01F ceramic decoupling capacitors as close to the power-supply pins as possible, and process the ECL outputs in microstrip fashion, consistent with the load termination of 50 to 200 (for VT = -2V). For low-impedance applications, microstrip layout and terminations at the input may also be helpful. Pay close attention to the bandwidth of the decoupling and terminating components. Chip components can be used to minimize lead inductance. Connect GND1 and GND2 together to a solid copper ground
plane for the MAX9691/MAX9692. GND1 biases the input gain stages, while GND2 biases the ECL output stage. If the LE function is not used, connect the LE pin to GND (MAX9692/MAX9693) and the complementary LE to ECL logic high level (MAX9693 only). Do not leave the inputs of an unused comparator floating for the MAX9693.
Input Slew-Rate Requirements
As with all high-speed comparators, the high gainbandwidth product of these devices creates oscillation problems when the input goes through the linear region. For clean switching without oscillation or steps in the output waveform, the input must meet certain minimum slew-rate requirements. The tendency of the part to oscillate is a function of the layout and source impedance of the circuit employed. Poor layout and larger source impedance will increase the minimum slew-rate requirement. Figure 1 shows a high-speed receiver application with 50 input and output termination. With this configuration, in which a ground plane and microstrip PC board are used, the minimum slew rate for clean output switching is 1V/s. In many applications, adding regenerative feedback will assist the input signal through the linear region, which will lower the minimum slew-rate requirement considerably. For example, with the addition of positive feedback components, Rf = 1k and Cf = 10pF, the minimum slew-rate requirement can be reduced by a factor of four.
5
VIN 50
Q Q LE 50 -2V 50 Rf Cf 50
Figure 1. Regenerative Feedback--High-Speed Receiver with 50 Input and Output Termination
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Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable MAX9691/MAX9692/MAX9693
trates two latch-enable pulses. Each pulse is high for the compare function and low for the latch function. The first pulse demonstrates the compare function; part of the input action takes place during the compare mode. The second pulse demonstrates a compare function interval during which there is no change in the input. The leading edge of the input signal (illustrated as a large-amplitude, small-overdrive pulse) switches the comparator after time interval tpd. Output Q and Q transistors are similar in timing. The input signal must occur at time ts before the latch falling edge, and must be maintained for time th after the edge to be acquired. After th, the output is no longer affected by the input status until the latch is again strobed. A minimum latch pulse width of tpw(LE) is needed for the strobe operation, and the output transitions occur after a time tLE(). The MAX9691/MAX9692/MAX9693 will not false trip (i.e., output invert) if one of the inputs is in the valid common-mode range while the other input is outside the common-mode range.
INPUT 20mV/div OUTPUT 500mV/div
0V
-0.9V -1.7V
2ns/div
Figure 2. Signal Processed at 100MHz with Input Signal Level of 14mVRMS
As high-speed receivers, the MAX9691/MAX9692/ MAX9693 are capable of processing signals in excess of 600MHz. Figure 2 is a 100MHz example with an input signal level of 14mVRMS. The timing diagram (Figure 3) illustrates the series of events that complete the compare function, under worst-case conditions. The top line of the diagram illus-
COMPARE LATCH ENABLE LATCH DIFFERENTIAL INPUT VOLTAGE ts th VIN t pw(LE) 50%
VOS VOD t pd t LE(+) 50%
Q
Q
50%
Figure 3. Timing Diagram 6 _______________________________________________________________________________________
Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable
Definition of Terms
VOS Input Offset Voltage. The voltage required between the input terminals to obtain 0V differential at the output. Input Voltage Pulse Amplitude Input Voltage Overdrive Input to Output High Delay. The propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output low-to-high transition. Input to Output Low Delay. The propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output high-to-low transition. Latch-Enable to Output High Delay. The propagation delay measured from the 50% point of the latch-enable signal low-to-high transition to the 50% point of an output low-to-high transition. Latch-Enable to Output Low Delay. The propagation delay measured from the 50% point of the latch-enable signal low-to-high transition to the 50% point of an output high-to-low transition. Latch-Enable Pulse Width. The minimum time the latch-enable signal must be high to acquire and hold an input signal. Setup Time. The minimum time before the negative transition of the latch-enable pulse that an input signal must be present to be acquired and held at the outputs. Hold Time. The minimum time after the negative transition of the latch-enable signal that an input signal must remain unchanged to be acquired and held at the output. Propagation Delay Skew. The difference in propagation delay between the Q and Q outputs crossing each other in both directions. Propagation Delay Dispersion. The change in propagation delay as a result of the overdrive of the input signal varying. Propagation Delay Match (MAX9693 only). The difference in propagation delay between two separate channels.
Chip Information
MAX9691 TRANSISTOR COUNT: 106 MAX9692 TRANSISTOR COUNT: 106 MAX9693 TRANSISTOR COUNT: 207
MAX9691/MAX9692/MAX9693
VIN VOD tpd+
tpd-
Ordering Information (continued)
PART MAX9692EUB MAX9692ESE MAX9692EPE MAX9693ESE MAX9693EEE MAX9693EPE TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 10 MAX 16 Narrow SO 16 PDIP 16 Narrow SO 16 QSOP 16 PDIP
tLE(+)
tLE(-)
tpw(LE)
ts
th
pd
PDSP
tpdm
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Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable MAX9691/MAX9692/MAX9693
Pin Configurations
TOP VIEW
MAX9692
VCC 1 IN+ INN.C. LE 2 3 4 5 10 GND1 9 8 7 6 GND2 Q OUT Q OUT VEE IN3 VCC IN+ 1 2
MAX9691
8 7 6 5 GND1 GND2 Q OUT Q OUT
VEE 4
MAX
DIP/SO/MAX
MAX9692
GND1 1 VCC 2 IN+ 3 IN- 4 N.C. 5 LE 6 N.C. 7 VEE 8 16 GND2 15 N.C. 14 N.C. 13 N.C. 12 Q OUT 11 Q OUT 10 N.C. 9 N.C. Q OUT 1 Q OUT 2 GND 3 LEA 4 LEA 5 VEE 6 INA- 7 INA+ 8
MAX9693
16 Q OUT 15 Q OUT 14 GND 13 LEB 12 LEB 11 VCC 10 INB9 INB+
PDIP/SO
DIP/SO/QSOP
8
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Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8L, MAX, EXP PAD.EPS
MAX9691/MAX9692/MAX9693
_______________________________________________________________________________________
10L UMAX, EXPPADS.EPS
9
Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable MAX9691/MAX9692/MAX9693
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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